may 2012 ?2012 fairchild semiconductor corporation FDME910PZT rev.c www.fairchildsemi.com 1 FDME910PZT p-channel powertrench ? mosfet FDME910PZT p-channel powertrench ? mosfet -20 v, -8 a, 24 m features ? max r ds(on) = 24 m at v gs = -4.5 v, i d = -8 a ? max r ds(on) = 31 m at v gs = -2.5 v, i d = -7 a ? max r ds(on) = 45 m at v gs = -1.8 v, i d = -6 a ? low profile: 0.55 mm maximum in the new package microfet 1.6x1.6 thin ? hbm esd protection level > 2 kv typical (note 3) ? free from halogenated compounds and antimony oxides ? rohs compliant general description this device is designed specifically for battery charging or load switching in cellular handset and other ultraportable applications. it features a mosfet with low on-state resistance and zener diode protection against esd. the microfet 1.6x1.6 thin package offers exceptional therma l performance for its physical size and is well suited to switching and linear mode applications. microfet 1.6x1.6 thin top bottom pin 1 d g d s d d 5 1 6 2 3 4 d d s d d g bottom drain contact mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage -20 v v gs gate to source voltage 8 v i d -continuous t a = 25c (note 1a) -8 a -pulsed -32 p d power dissipation t a = 25c (note 1a) 2.1 w power dissipation t a = 25c (note 1b) 0.7 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 60 c/w r ja thermal resistance, junction to ambient (note 1a) 175 device marking device package reel size tape width quantity e91 FDME910PZT microfet 1.6x1.6 thin 7 ?? 8 mm 5000 units
www.fairchildsemi.com 2 ?2012 fairchild semiconductor corporation FDME910PZT rev.c FDME910PZT p-channel powertrench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = -250 a, v gs = 0 v -20 v bv dss t j breakdown voltage temperature coefficient i d = -250 a, referenced to 25 c -16 mv/c i dss zero gate voltage drain current v ds = -16 v, v gs = 0 v -1 a i gss gate to source leakage current v gs = 8 v, v ds = 0 v 10 a v gs(th) gate to source threshold voltage v gs = v ds , i d = -250 a -0.4 -0.6 -1.5 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = -250 a, referenced to 25 c 2.7 mv/c r ds(on) static drain to source on resistance v gs = -4.5 v, i d = -8 a 20 24 m v gs = -2.5 v, i d = -7 a 25 31 v gs = -1.8 v, i d = -6 a 32 45 v gs = -4.5 v, i d = -8 a,t j = 125c 26 36 g fs forward transconductance v dd = -5 v, i d = -8 a 38 s c iss input capacitance v ds = -10 v, v gs = 0 v, f = 1 mhz 1586 2110 pf c oss output capacitance 236 355 pf c rss reverse transfer capacitance 218 330 pf t d(on) turn-on delay time v dd = -10 v, i d = -8 a, v gs = -4.5 v, r gen = 6 918ns t r rise time 11 20 ns t d(off) turn-off delay time 87 139 ns t f fall time 46 74 ns q g total gate charge v gs = -4.5 v, v dd = -10 v, i d = -8 a 15 21 nc q gs gate to source charge 2.2 nc q gd gate to drain ?miller? charge 3.6 nc v sd source to drain diode forward voltage v gs = 0 v, i s = - 8 a (note 2) -0.8 -1.2 v v gs = 0 v, i s = -1.8 a (note 2) -0.7 -1.2 v t rr reverse recovery time i f = -8 a, di/dt = 100 a/ s 17 31 ns q rr reverse recovery charge 4.1 10 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. the diode connected between the gate and source serves only as protection esd. no gate overvoltage rating is implied. a. 60 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 175 c/w when mounted on a minimum pad of 2 oz copper.
www.fairchildsemi.com 3 ?2012 fairchild semiconductor corporation FDME910PZT rev.c FDME910PZT p-channel powertrench ? mosfet typical characteristics t j = 25 c unless otherwise noted figure 1. 0123 0 8 16 24 32 v gs = -2.5 v v gs = -1.8 v v gs = -1.5 v v gs = - 3 v pulse duration = 80 p s duty cycle = 0.5% max v gs = -4.5 v -i d , drain current (a) -v ds , drain to source voltage (v) on region characteristics figure 2. 0 8 16 24 32 0 1 2 3 v gs = -1.8 v v gs = -2.5 v v gs = -1.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance -i d , drain current (a) v gs = -4.5 v v gs = -3 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 i d = -8 a v gs = -4.5 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 40 80 120 t j = 125 o c i d = -8 a t j = 25 o c -v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0.5 1.0 1.5 2.0 0 8 16 24 32 t j = 150 o c v ds = -5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c -i d , drain current (a) -v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v -i s , reverse drain current (a) -v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 4 ?2012 fairchild semiconductor corporation FDME910PZT rev.c FDME910PZT p-channel powertrench ? mosfet figure 7. 0481 21 6 0.0 1.5 3.0 4.5 i d = -8 a v dd = -12 v v dd = -8 v -v gs , gate to source voltage (v) q g , gate charge (nc) v dd = -10 v gate charge characteristics figure 8. 0.1 1 10 20 100 1000 3000 f = 1 mhz v gs = 0 v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 03691215 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 v ds = 0 v t j = 25 o c t j = 125 o c -v gs , gate to source voltage (v) -i g , gate leakage current (a) g a t e l e a k a g e c u r r e n t vs gate to source voltage f i g u r e 1 0 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100 0.01 0.1 1 10 50 1 s 10 ms dc 10 s 100 ms 1 ms -i d , drain current (a) -v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 175 o c/w t a = 25 o c figure 11. single pulse maximum power dissipation typical characteristics t j = 25 c unless otherwise noted 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.1 1 10 100 p (pk) , peak transient power (w) single pulse r t ja = 175 o c/w t a = 25 o c t, pulse width (sec)
www.fairchildsemi.com 5 ?2012 fairchild semiconductor corporation FDME910PZT rev.c FDME910PZT p-channel powertrench ? mosfet figure 12. 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.001 0.01 0.1 1 single pulse r t ja = 175 o c/w (note 1b) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 6 ?2012 fairchild semiconductor corporation FDME910PZT rev.c FDME910PZT p-channel powertrench ? mosfet dimensional outline and pad layout
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